From copper to optics

Best-in-class for enterprise, cloud & 5G infrastructure​

Minimum Downtime for infrastructure​

Outdoor as well as Indoor​

Enhance customer competitiveness​

System bring-up in no time​

Technology

eTopus is the pioneer of ADC-based DSP system architecture for ultra-high speed wireline applications

eTopus has built from the ground up an advanced system architecture to deliver superior Bit Error Rate (BER) performance for Long Reach applications. The advanced architecture developed is called eTopus Partial-Response Technology (ePRTTM) architecture. It is a highly programmable and adaptive Receiver DSP architecture, which is fully compatible with existing standards. This innovative architecture is proven with multiple generations of silicon and was tested extensively and collaboratively with our lead customers for performance, robustness, standard compliance, and interoperability.

Scalability

1-112G wide data rate range​
0-35dB wide insertion loss range​
Low and scalable power consumption​​​​

Reliability

ePRT™ equalizes any closed RX eyes​
Superior pre- and post-FEC Bit Error Rate​
Minimal DFE error propagation​

Robustness

CDR maintains lock even at 1% BER​
Patented T.I. ADC phase calibration​
Excellent supply noise immunity​​​​

Temperature

Wide range -40 to 125oC Tj support​
Fast adaptation tracking at 10oC/minute w.r.t. temperature ramping​

Cost

Dual power-rail minimizes system cost​
Direct Optical Drive saves external retimer​
Extended LR saves external retimer​

eZ-API

eZLINK™ locks to any random data​
IEEE AN/LT protocol compliance
Easy chip integration and bring-up​

Customer Use Cases

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Enterprise– Minimize system cost

High switching density and cost are the driving factors in enterprise networking

  • Extended LR supports longer backplane, direct attached cable; eliminates external retimers
  • DSP architecture enables direct optical drive; eliminates external retimers
  • Dual power-rail simplifies package design, reduces external voltage regulator cost

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Data Center – Rapid silicon bring-up

Bringing up hundreds of lanes for high-density switch is a big headache

  • Extensive software support through Software Development Kit (SDK)
  • Comprehensive API for SerDes firmware control
  • Proprietary algorithm brings up SerDes lanes rapidly with optimal performance

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AI – Low Latency chip-to-chip interconnect

Data Center applications require reliable Ethernet connection

  • SerDes is latency optimized
  • Superior BER with minimal DFE burst errors

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Data Center – Composable Disaggregated Infrastructure

Data Center applications require reliable Ethernet connection

  • Superior pre- and post-FEC Bit Error Rates (BER) over Direct Attached Cable (DAC Cables) or Optical Links
  • Proprietary algorithm (eZLINK™) that rapidly locks to any random data in sub-millisecond range

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5G – Fast temperature tracking

Outdoor 5G applications demand wide temperature support

  • Temperature support from -40oC to 125oC Tj
  • Fast adaptation and smooth temperature tracking at 10oC per minute
  • Robust Clock Data Recovery (CDR) – maintain lock even at 1% BER

References

Paper:

Published in 2021 ISSCC – A Scalable Adaptive ADC/DSP-Based 1.25-to-56Gbps/112Gbps High-Speed Transceiver Architecture Using Decision-Directed MMSE CDR in 16nm and 7nm – eTopus 8.5

Patents:

  • Receiver with adjustable reference voltages – US9742422B2
  • Receiver with adjustable reference voltages – US9397680B2
  • Sampling clock adjustment for an analog to digital converter of a receiver – US9425950B2
  • Timing recovery for digital receiver with interleaved analog-to-digital converters – US9780796B2
  • Timing recovery for digital receiver with interleaved analog-to-digital converters – US9461654B1
  • Receiver for high speed communication channel – US10680857B2
  • Receiver for high speed communication channel – US10270627B2
  • Receiver for high speed communication channel – US9319249B2
  • Multi mode viterbi decoder – US9705531B2
  • ADC reconfiguration for different data rates – US10720936B1
  • ADC reconfiguration for different data rates – US10931295B2
  • ADC slicer reconfiguration for different channel insertion loss – US011115040B1